SVT Readout System Description
Year 1 System

- generates the acquisition sequence with 80 to 100μs delay, digital reset, analog reset, analog reset recovery, 80 adcClk, 81 scaClk, cycled 128 times. Starts fiber transfer after small delay

· Fibre State machine

- generates fiber transfer commands, start header, start data, end-of-data and raises CAV to FOB. It also triggers AMB1 to start fiber-data transfer.

· Slow controls State Machine

- Interpret & acknowledge HDLC commands

SVT Trigger Functions

Board Description: PTBA

· PTBA Inputs and Outputs

· Schematic Diagram in pdf format

· Picture of the board

PTBA Functions

· Receives one set of SCA control signals from PTB and generates 6 sets to the Transition Boards via the panel (LVDS)

· LVDS part: National DS90C031 Quad CMOS Differential Line Driver

· Generates & controls 2 sets of hybrid voltages

· Provides Slow Controls data path (8bit) to panel

Fusing

Board Description: AMB

· AMB Inputs and Outputs

· Schematic Diagram in pdf format

· Picture of the board

AMB Functions

· Digitizes 12 channels of analog data

- Organized as 3 groups of 4 channels to service 4 hybrids with 3 channels each

· ADC threshold and range adjustable

- Standard: 0.8 - 1.2V threshold, 2V range

· Stores data in one of two SRAM memory banks as 40-bit words

· One of the 5 AMBs is also used to store the complete header to be sent to DAQ

· Transfers either bank of data memory to the FOB over a 40-bit data bus

· Memory can also be read and written over slow controls data bus in 16-bit chunks via a transfer register

AMB Major Parts

· Twelve Texas Instruments 10-bit, 20MSPS ADC’s TLC876C (AD876 “equivalent”)

· Twelve Analog Devices high-speed op-amps AD817AR

· Five Motorola 128K x 8bit Fast SRAM MCM6726B

· Altera PLD EPM7256SQC208-10

AMB Firmware

· D/A State Machine

- reads three sets of four ADC into memory separated by 80 words for 128 by 240 - 40bit values. The 240 are on 256 word boundaries

· Fiber State Machine

- provides 9-step timing to sync with the nine 20bit fiber transfers. AMB1 sends a sync pulse to the other 4 AMBs. Transfers both header (AMB-1 only) and data to FOB, one (40bit) word per cycle every two steps, on different steps for each AMB. Only 20 bits are valid for AMB5, using only 1 step. AMB-1 provides Data Valid (DAVA) signal to other AMBs

· Header State Machine (AMB-1 only)

- Transfers header from PTB to memory

· Slow Controls State Machine

- Interpret and acknowledge SC commands

Board Description: FOB

· FOB Inputs and Outputs

· Schematic Diagram in pdf format

· Picture of the board

FOB Functions

· Receives 40-bit words from AMBs and multiplexes these as two 20-bit words to the HP Gigalink serializer

· Transfers data to DAQ via Finisar/Methode Fiber-Optic transmitter

· Logic is driven by PTB control words

· Gigalink runs at 60MHz

· Receives 60MHz clock from PTB and distributes it to the AMBs

· For testing the FOB can be equipped with its own clock crystal to operate the Gigalink

FOB Major Parts

· HP Gigalink TTL Transmitter HDMP1022

· Finisar / Methode Fiber Transmitter FTM-8510-2-0 / MTM-8510-SC

· Altera PLD EPM7128SLC84-6

FOB Firmware

· Startup State Machine

- provides reset to the HP chip at start-up

· Fiber Control State Machine

- transfer control words from PTB to HP chip

· Fiber Data State Machine

- Transfer header data from AMB1 and ADC data from the 5 AMBs

Board Description: RDO Panel

RDO Panel Functions

· Provides all RDO connectors to outside world except fiber (directly on FOB)

· Distribute 3 Transition Board analog signals to 5 AMBs in 2 configurations, selectable with a jumper

· Circuitry for multiplexing and digitizing:

- 3*6 + 2 voltages

- 3*5 currents

- 3*4 temperatures + 3*4 detector currents

· Latch 3 Transition Board IDs (6 bits each, 1 bit provided via jumper on panel) read as 8-bit words (1 spare bit)

· Power drivers & controls for 3*6 calibration lines

RDO Panel Major Parts

· Micrel Quad Power Drivers MIC4467

· Analog Devices 16-channel Multiplexers ADG426

· Analog Devices 8-bit ADC AD7575

RDO Configurations

Slow Controls

Slow Controls Functions

· Panel Slow Controls to monitor multiplexed:

- 3*6 + 2 voltages

- 3*5 currents

- 3*4 temperatures + 3*4 detector currents

· Panel Read 3 Transition Board Ids

· Panel Control 3*6 Calibration Lines

· PTB & PTBA switch 3*6 FEE voltages

· PTB trigger fiber optic readout with & without ADC acquisition

· AMB memory read/write (read as 16/16/8 bit chunks from a latching register)

· AMB bank selection for stored event R/O

Slow Controls Implementation

· Bieser HDLC mezzanine on PTB board

· Provides both HDLC and Serial interface (RS232 driver on PTB)

· ID bits set via jumper on PTB

· Use Chip-Select 3 memory region only

· Control signals from mezzanine used:

- R/W

- CS3

- DTAck

- DS not used, but doesn’t seem to be necessary

· Use A16 - A19 for board selection

· Use A1 - A4 for function selection

· HDLC 16-bit data bus on VME back plane connected to all boards

· Panel connected to VME through PTBA via 8-bit bus, control signals from PTB

Slow Controls Implementation Block Diagram

HDLC Memory Map (STAR wide)

RDO HDLC Memory Maps

Board Offsets:

Board	Address Offset
AMB-1	0x080 000
AMB-2	0x090 000
AMB-3	0x040 000
AMB-4	0x0d0 000
AMB-5	0x0c0 000
PTB	0x050 000
FOB	0x0f0 000

PTB Decodes:

Address	I/O Cycle	Action
0x050 000	W	Load TB-1 low-voltage power register
0x050 002	W	Load TB-2 low-voltage power register
0x050 004	W	Load TB-3 low-voltage power register
0x050 006	W	Load TB-1 injector register
0x050 008	W	Load TB-2 injector register
0x050 00a	W	Load TB-3 injector register
0x050 00c	W	Load MUX-1
0x050 00e	W	Load MUX-2
0x050 010	W	Start ADC conversion & fibre transfer
0x050 012	W	Start fibre transfer (no ADC conversion)
0x050 014	W	Issue L2-accept
0x050 016	R	Pulse/read instrumentation ADC
0x050 018	R	Read ID-1 input bits
0x050 01a	R	Read ID-2 input bits
0x050 01c	R	Read ID-3 input bits

Low-voltage power register bits:

Bit	Voltage	1	0
Q0
Q1	V1	On	Off
Q2	V2	On	Off
Q3	V3	On	Off
Q4	V-	Off	On
Q5	-6	Off	On
Q6	+6	On	Off
Q7

MUX-1 and MUX-2 load data into registers U14, U15, U16, U17, U22 and U23. The outputs of U14 and U15 are connected to an instrumentation ADC for digitization. The outputs of the other registers are connected to different inputs of U15. Data needs to be loaded into these registers before the ADC can be used. The ADC requires two read cycles for a complete readout: the first read cycle digitizes the current input to the ADC, while the second read cycle gates out the results. The second read cycle can be used as the first read cycle (“digitization”) of the next readout, thus allowing pipelining of the readout of several signals.

MUX-1 bits:

Bit	Meaning
0	Data-bit-3
1	Data-bit-2
2	Data-bit-1
3	Data-bit-0
4	Enable U15
5	Enable U14
6
7

MUX-2 bits:

Bit	Meaning
0	Data-bit-0
1	Data-bit-1
2	Data-bit-2
3	Data-bit-3
4	Enable U17
5	Enable U16
6	Enable U23
7	Enable U22

Data	U14	U15	U16	U17	U22/23
0	T2T1	U16	T1V1	T1-6	T1I1
1	T2T2	U17	T1V2	T1V-	T1I2
2	T2T3	U22/23	T1V3	T2-6	T1I-
3	T2T4		T1+6	T2V-	T1I+6
4	T2T5		T2V1	T3-6	T2I1
5	T2T6		T2V2	T3V-	T2I2
6	T2T7		T2V3	-8	T2I-
7	T2T8		T2+6		T2I+6
8	T1T1	T3T1	T3V1		T3I1
9	T1T2	T3T2	T3V2		T3I2
A	T1T3	T3T3	T3V3		T3I-
B	T1T4	T3T4	T3+6		T3I+6
C	T1T5	T3T5	+8		T1I3
D	T1T6	T3T6	SpareT11		T2I3
E	T1T7	T3T7	SpareT21		T3I3
F	T1T8	T3T8	SpareT31

Note: U22/23 measure currents, and need to be loaded with the same data and enabled at the same time to make sensible measurements.

AMB Decodes:

Address	I/O Cycle	Action
0x0X0 000	W	Load page register (0..3)
0x0X0 002	W	Load address register bits 0..7
0x0X0 004	W	Load address register bits 8..15
0x0X0 006	W	Write transfer register least significant16 bits (ls16)
0x0X0 008	W	Write transfer register middle 16 bits (m16)
0x0X0 00a	W	Write transfer register most significant 8 bits (ms08)
0x0X0 00c	R	Read transfer register ls16
0x0X0 00e	R	Read transfer register m16
0x0X0 010	R	Read transfer register ms08
0x0X0 012	W	Write memory to transfer register (40-bits)
0x0X0 014	W	Write transfer register to memory (40-bits)